1. Field of the Invention.
The present invention relates to the field of electrically programmable and electrically erasable memory cells and more particularly the erase of memory cells employing floating gates.
2. Prior Art.
The fabrication of electrically programmable read-only memories (EPROMs) utilizing metal-oxide-semiconductor (MOS) techology is well-known in the prior art. These EPROMs employ memory cells utilizing floating gates which are generally formed from polysilicon members completely surrounded by an insulator. Electrical charge is transferred into the floating gate using a variety of techniques such as avalanche injection, channel injection, Fowler-Nordheim tunnelling, channel hot electron injection, etc. A variety of phenomena have been used to remove charge from the floating gate including exposing the memory to ultraviolet radiation. The floating gate is programmed when a charge is stored in the floating gate. The cell is in an unprogrammed, or erased, state when the floating gate is discharged.
Because of complex and time consuming procedures required to erase EPROMs, these devices have been used primarily in applications requiring read-only memories. Electrically programmable and electrically erasable read-only memories (EEPROMs) were developed to provide the capability of electrically erasing programmed memory cells. These EEPROMs have also been referred to as electrically alterable read-mostly memories. Commercially available EEPROMs have generally used a thin oxide region to a transfer the charge into and from a floating gate. In a typical memory, a two-transistor cell is used. For instance, U.S. Pat. No. 4,203,158 discloses the fabrication of such an EEPROM cell. Further, U.S. Pat. No. 4,266,283 discloses the arrangement of EEPROMs into an array wherein X and Y select lines provide for the selection, programming and reading of various EEPROM cells. These EEPROM cells do not lend themselves to being reduced in substrate area as due the EPROM cells.
Various techniques have been implemented to reduce the size of the memory array by providing higher density cells. One such technique is disclosed in U.S. Pat. No. 4,432,075. Further, the use of a single 5 volt potential supply to provide the requisite current and voltage for the proper operation of EEPROMs is crucial to the manufacture of the more recent EEPROM technology. U.S. Pat. No. 4,432,075 discloses the sharing of a single source of hot electrons by a number of cells to provide the additional current required for programming the various cells. Further, the use of a single 5 volt external supply to generate on-chip a higher potential which is required for programming is known in the prior art.
A further attempt to provide higher density, low voltage EEPROM cell is disclosed in a U.S. patent application, Ser. No. 892,446 filed Aug. 4, 1986 and entitled Low Voltage EEPROM Cell and is assigned to the assignee of the present application. In this copending application, a one-transistor EEPROM cell which uses channel injection for charging the floating gate and tunnelling for discharging the gate is disclosed. A single 5 volt potential is used with a higher programming/erasing potential of approximately 11-15 volts being generated on-chip. However, the EEPROM of the one-transistor design uses the same transistor and the same oxide separating the transistor elements from the floating gate to both program and erase the floating gate. Because of the one-transistor design, over-erased condition of a memory cell is more prevalent than in the two-transistor design. An over-erase condition must be avoided in order to prevent the one-transistor EEPROM memory cell from becoming a depletion-like transistor in the read mode. During the read mode an over-erased memory cell will disable a whole column of a memory array if the memory cells are structured as an array. The over-erase problem is not typically a concern with the two-transistor design or the quasi-one-transistor EEPROM design, which is disclosed in a copending patent application, Ser. No. 009,998 filed Feb. 2, 1987 which is also assigned to the assignee of the present invention. However, again, the two-transistor design will required much bigger cell area while the quasi-one-transistor EEPROM described in the Ser. No. 009,998 reference requires more processing steps.
The present invention provides for a scheme to self-limit the electrical erase of a single transistor floating gate EEPROM cell, wherein whole arrays are not disabled due to an over-erase condition of a single EEPROM cell.